Current biasing circuits, or "current mirror" circuits, are generally well known. Current mirrors generally use transistors, FETs (Field-Effect Transistors) or BJTs (Bipolar Junction Transistors), to produce a controlled current in a "biased" device as a multiple of a reference current that flows in a "reference" device. In an ideal case, the multiplying factor depends only upon the geometrical properties of the reference and the biased device.
Current mirrors constructed of conventional transistor devices should come close to the ideal case, where the physical geometry of the transistors is the sole factor influencing errors. Transistors typically used in current mirror devices include MOSFET (Metal Oxide Semiconductor Field-Effect Transistor), MESFET (Metal Semiconductor Field-Effect Transistor), HEMT (High-Electron-Mobility Transistor) and PHEMT (Pseudomorphic High-Electron-Mobility Transistor) devices. The operation of these transistors is based upon the strength of an electrical field in a "channel" underneath a "gate" region. In the ideal case, inaccuracies in the current multiplication factor should relate back only to lithographic errors, which are unavoidable in semiconductor device manufacturing. However, the lithographic errors can be minimized.
If the electrical device transfer functions are ideal, in the sense that differences in the electrical environment or temperature of the reference device and the biased device do not influence the current multiplication factor, then the geometrical errors of the devices define the accuracy limit that can be achieved. However, this is not generally the case, particularly in advanced transistor devices with very short channel lengths; the channel length being the physical length of the gate contact. Various operational parameters influence the current multiplication factor in traditional current mirror devices.
For instance, short channel effects, which result from channel length modulation due to changes in the transistor's drain-source voltage, effect the current multiplication ratio. Velocity saturation effects, which depend on the transistor's drain-source voltage and result from the limited drift velocity of charge carriers in the channel region of the transistor substrate, also effect the current multiplication ratio. Threshold voltage modulation effects also influence the current multiplication ratio. The threshold voltage modulation effects generally result from either a barrier lowering effect caused by increasing drain-source voltage in short channel length transistors, or a barrier increasing effect, particular to short channel length silicon MOSFET transistors, caused by increasing source-bulk voltage. Still further, drain-gate reverse leakage current, common to FETs, has an effect on the current multiplication ratio. The drain-gate leakage current typically results from reverse leakage, including tunnelling, in the gate-source Schottky contact in MESFET devices, or tunnelling through the gate oxide region in MOSFET devices.
The present invention is directed toward overcoming one or more of the above-mentioned problems.